1. Field of the Invention
The present invention provides a conductive structure and method for forming the conductive structure, and more particularly, to a conductive structure for a semiconductor chip and a method for forming the conductive structure.
2. Descriptions of the Related Art
Flip-chip packaging technology is mainly used to flip the front surface of a chip over and then join the bumps of the chip with the pads of a substrate so that the bumps are used as electrical conduction paths between the chip and the substrate. Because the bumps can be uniformly distributed on the whole chip with fine spacing between the bumps, this can effectively reduce the packaging volume and increase the circuit density. Therefore, flip-chip packaging technology has been widely used in microprocessor packages, graphic chips, computer chips, etc.
FIGS. 1A to 1C are schematic top views illustrating a semiconductor structure 1 and process of forming the semiconductor structure 1 of the prior art. FIGS. 1A′ to 1C′ are schematic side views corresponding to FIGS. 1A to 1C respectively.
First, with referring to both FIGS. 1A and 1A′, the semiconductor structure 1 consists of a substrate 11, a plurality of pads 12, a passivation layer 13 and an under bump metal layer 14. After the conventional pads 12 are arranged on the substrate 11 equidistantly and adjacent to each other, an insulation layer 15 is disposed to cover the under bump metal layer 14, and then a plurality of rectangular openings 151 are formed in the insulation layer 15 to allow bumps 16 to be respectively implanted therein. As shown in FIGS. 1B and 1B′, after the bumps 16 are disposed in the openings 151, excess portions of the insulation layer 15 can be removed to expose the under bump metal layer 14.
Finally, as shown in FIG. 1C and FIG. 1C′, the under bump metal layer 14 except for portions thereof that are located beneath the bumps 16 are removed through an etching process to expose the passivation layer 13 to prevent electrical conduction between chip components in the substrate 11 and external components through the under bump metal layer 14.
As shown in FIGS. 1B and 1B′, a spacing distance 161 exists between the bumps 16. The projection areas formed by two adjacent and alternately arranged bumps 16 which are projected onto each other have an overlapping area A1. In the aforesaid etching process, because the spacing distance 161 between the conventional bumps 16 is too small and each of the overlapping areas A1 are elongated, the etchant cannot effectively permeate into spacing distance 161. However, the area A2 around the bumps 16 is relatively wide. Consequently, the reaction rate of the etchant in the wide area A2 is higher than the reaction rate of the etchant in the overlapping areas A1. Due to the uneven etching of the under bump metal layer 14 among the overlapping areas A1, a part of the under bump metal layer 14 will remain on the substrate and, moreover, excessive etching might also cause deformation of the bumps 16 to affect the quality of the overall semiconductor structure 1.
Accordingly, it is important to provide a conductive structure for a semiconductor chip capable of overcoming the aforesaid shortcomings.